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Test equipment

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Test equipment

Physical layer (PHY)

Semiconductors; Test equipment

The bottom layer of the OSI and ATM protocol stack, which defines the interface between the different physical media. The PHY consists of two sublayers: the transmission convergence (TC) sublayer and ...

Photochemical hole burning (PHB)

Semiconductors; Test equipment

An optical memory technique, in which a laser in the visible waveband is directed at a microscopic point on the surface of a slice of glass which has been doped with organic dyes or rare-earth ...

Power factor correction (PFC)

Semiconductors; Test equipment

A technique of counteracting the undesirable effects of electric loads that create a power factor (p.f.) that is less than 1. Power factor correction may be applied either by an electrical power ...

Power factor (PF)

Semiconductors; Test equipment

Power factor is defined by IEEE and IEC as the ratio of true power to apparent power: PF = W/VA. where: W = true power (sometimes called active power or real power) in watts measured with a ...

Pad grid array (PGA)

Semiconductors; Test equipment

Similar to a pin grid array. An IC package that has solderable connexions in a grid layout on the bottom of the package, and is soldered to the surface of the substrate (PWB) with butt solder joints.

PCI Industrial Computer Manufacturers Group (PICMG)

Semiconductors; Test equipment

The group of member companies that maintains current specifications for CompactPCI and PCI/ISA.

Pin grid array (PGA)

Semiconductors; Test equipment

A pin grid array refers to a packaging technology in which a device's external connexions are arranged as an array of conducting leads, or pins, on the base of the package.

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